Tutorial: Partial Reconfiguration of FPGAs in Practice - Tools and Applications

Run-time reconfiguration of FPGAs has been around in academia for more than two decades but it is still applied very seldom in industrial applications. This has two main reasons: a lack of killer applications that substantially benefit from run-time reconfiguration and design tools that permit to quickly implement corresponding reconfigurable systems.

This tutorial gives a survey on state-of-the-art trends on reconfigurable architectures and devices, application specific requirements, and design techniques and tools that are essential for implementing partial run-time reconfiguration on FPGAs. This is followed by a live demonstration of the floorplanning and constraint generation tool GoAhead.

Furthermore, the tutorial will reveal several applications that benefit from partial reconfiguration, including network data processing, digital signal processing, and systems on a reconfigurable chip. For these applications, the individual challenges and implementation issues are presented together with the achieved results. This tutorial demonstrates that partial FPGA reconfiguration is beneficial and applicable in industrial systems.

Target audience:

all

Level:

introductory

Presenters

Dirk Koch

University of Oslo, Norway
koch@ifi.uio.no
+47 22 84 42 42

Jim Torresen

University of Oslo, Norway
jimtoer@ifi.uio.no
+47 22 85 25 54

Christian Beckhoff

ReCoBus, Germany
Christian@recobus.de
+49 (0) 911 47 81 911

Daniel Ziener

University of Erlangen, Germany
daniel.ziener@informatik.uni-erlangen.de
+49 (0) 91 31 85 25 14 5

Christopher Dennl

University of Erlangen, Germany

Volker Breuer

University of Erlangen, Germany

Juergen Teich

University of Erlangen, Germany
teich@informatik.uni-erlangen.de
+49 (0) 91 31 85 25 15 0

Michael Feilen

Technische Universitaet Muenchen, Germany
michael.feilen@tum.de
+49 (0) 89 28 92 38 73

Walter Stechele

Technische Universitaet Muenchen, Germany
walter.stechele@tum.de
+49 (0) 89 28 92 25 15